1. Field of the Invention
The present invention relates to a buffer device, a buffer arrangement method, and an information processing apparatus.
2. Description of the Related Art
A data buffer (hereinafter, ‘buffer device’) is conventionally used for data transfer between a central processing unit (CPU) core and a peripheral device (such as a cache memory or an external interface). The buffer device serves to absorb the difference in the bus width between the data paths of the data source and the data destination as well as to temporarily store a plurality of pieces of transfer data.
With the ongoing improvement of the processing speed of the CPU core, the demand has been increasing for improving the data transfer speed between the CPU core and the peripheral devices. Various technologies, such as parallelization of data transfer and parallelization of line buffers built in a buffer device, have been proposed to enhance the data transfer speed.
For example, Japanese Patent Application Laid-open No. H02-82330 discloses a technology wherein a buffer device is provided between a CPU core and a peripheral device (such as a cache memory or an external interface) for transferring data that is divided into a plurality of lines to be output in parallel by the CPU core to the peripheral device after buffering the data in a plurality of line buffers provided for each line.
However, the technology is described on the premise that there is only one CPU core. Sharing one buffer device by a plurality of CPU cores may cause the difference in length of wirings connecting between each CPU core and the line buffers, which results in having an adverse effect on the processing speed of the CPU cores. Specifically, the data transfer speed is greater for shorter wiring lengths. If there are varying wiring lengths, the data transfer speed needs to be adjusted to suit the longest wiring length.
For example, when there are two CPU cores A and B, if the longest wiring length A between a CPU core A and the line buffers is not equal to the longest wiring length B between a CPU core B and line buffers is B, the data transfer rate has to be reduced to suit the greater of the longest wiring lengths A and B.
To enhance the reliability of a CPU chip, it is preferable to minimize interference of wirings with each other by reducing their number. However, wiring interference is a natural consequence of a plurality of CPU cores sharing a buffer device.
Therefore, it is a challenge to realize a buffer device shared by a plurality of CPU cores in which the difference in the wiring length is minimized and wiring interference between the wirings connecting the CPU core and the line buffers is reduced.